Digital logic circuits are of two basic types, combinational and sequential. Combinational logic circuits generate an output signal asynchronously in response to at least one input signal. That is, they provide the output signal as soon as the input signals propagate through the circuit. Sequential logic circuits, on the other hand, require clocking or timing information in order to perform logic functions. While combinational logic circuits are important building blocks in integrated circuit design, almost all digital integrated circuits use at least some sequential logic circuits. In addition, some analog integrated circuits, such as those having switched capacitor filters, also require clocking information.
With increasing speeds of integrated circuits, there arises the need to have more and more precise clocking signals. Normally these integrated circuits receive a digital clock input signal, and then buffer the clock input signal before providing it to internal circuits. During one part of the clock period, the clock signal is at a logic high voltage, and during another part of the clock period, the clock signal is at a logic low voltage. The rest of the clock period is made up of transitional states between a logic high and a logic low voltage.
In most applications, it is desirable for these integrated circuits to receive a clock which has 50/50 duty cycle, i.e., has its logic high time equal to its logic low time in each clock period. However, as integrated circuits become faster and faster, signal propagation delay through logic gates in the clock buffers becomes a greater percentage of the clock period. This can cause the duty cycle to change from 50/50 if the logic circuit which generates the clock signal has a bias toward one logic state.
A significant source of this duty cycle error originates from conversion from analog (continuous) waveforms to digital signals of either 1 or 0 value inside the clock generator circuit. The analog-to-digital conversion is frequently performed with a comparator followed by cross-coupled NAND gates. The comparator amplifies the small amplitude analog signal into nearly digital values. The cross-coupled NAND gates complete the conversion to fully digital signals. This method of obtaining digital values is satisfactory, but the cross-coupled NAND gates introduce a systematic duty cycle error. This error is created because the network of cross-coupled gates has rise and fall times that are an unequal number of gate delays. This fact introduces a duty cycle error of one gate delay that is equal to the difference in number of gate delays for rising and falling signals. This gate delay asymmetry becomes a significant fraction of the clock period as frequencies increase and lower supply voltages increase gate delay times.